1. Field of the Invention
The present invention relates to a transponder used for the RFID (Radio Frequency Identification) system and, in particular, to a non-volatile ferroelectric memory, a drive method and an ID card thereof, which contains a memory cell array employing a ferroelectric layer for an information memory capacitor mounted on the transponder.
2. Discussion of the Background
The RFID system is referred to as a non-contact tag system (identifier) using electronic waves, which comprises a personal computer, a controller, antennas etc. The transponder contains chips such as a non-volatile ferroelectric memory and so on. Recently there has been much development and research activity related to the non-volatile ferroelectric memory for use in semiconductor memory devices with low power consumption. This non-volatile ferroelectric memory is described, for example, in U.S. Pat. No. 4,873,664 to Eaton, Jr. and S. S. Eaton, Jr. et al. "A Ferroelectric DRAM Cell for High Density NVRAMs", ISSCC Digest of Technical Papers, pp-130-131 (February 1988).
The memory capacitor for the ferroelectric memory cell consists of barium titanate acid (BaTiO.sub.3), lead zirconium titanate acid (Pb (Zr, Ti)O.sub.3 ; PZT), lanthanum doped lead zirconium titanate acid (Pb, La) (Zr, Ti)O.sub.3 ; PLZT), lithium niobium acid (LiNbO.sub.3), potassium lithium niobium acid (K.sub.3 Li.sub.2 Nb.sub.5 O.sub.15) etc. These ferroelectric layers are polarized when a voltage is applied. The relation between voltage and polarization also exhibits a hysteresis property.
Regarding this relation, when the inventor measured the properties of the aforesaid ferroelectric layers, it was found that externally applied physical stress causes changes in the properties of the aforesaid hysteresis property. In other words, when physical stress was applied to the ferroelectric layer after it is formed, it was found that hysteresis property becomes worse and the value of polarization is deteriorated. The ferroelectric memory uses polarization for data holding. Accordingly, it is obvious that physical stress results in deterioration of the data holding properties.
FIG. 1(a) shows an arrangement of a conventional non-volatile semiconductor device memory cell array and peripheral circuits. Plural memory arrays are arranged in parallel, and the row decoder (word line selector circuit) 40 is used together therewith. Plural word lines (WL) are selected according to an address signal from the outside. The plate line (PL) is connected to the memory cell array (to a plate electrode of the cell capacitor), and driven by the plate decoder (plate line select circuit) 38 in the same manner as word line WL. Plate decoder 38 comprises a NAND circuit and an inverter circuit in series, and controls the plate electrodes by a logical operation of the word line signal and plate line control signal. A write signal or read signal through the word line or the plate line is a pulse signal. However, the pulse duration of the plate line signal to control the plate line signal is shorter than that of the word line signal, as shown in FIG. 1(b). Thus, since the plate line signal rises and falls in a short time, a read speed of the memory cell will be controlled by the plate signal pulse. The plate line, on the other hand, is connected in common to the aforesaid plate electrodes on the cell capacitors. In contrast, the word line is only connected to the transistor gate, and as a result the load capacity is very high. Thus, it takes a longer time to activate the plate line, compared to activating the word line. As a result, since the plate line is activated with a delay, it is impossible to obtain enough time to read all of the written data. It may also happen that the data can not be written completely in the cell. In order to avoid these troubles, it is necessary to increase the driving capability of a transistor in the inverter circuit in the plate line selector circuit 38. However, if the driving capability is unnecessarily increased, a word line driver pitch does not match with a plate line selector pitch for the row decoder circuit. A greater clearance between the word line and plate line is influenced by a smaller clearance between the word line and plate line, and the resulting area loss will occur.
As explained above, for a non-volatile ferroelectric memory used in a conventional transponder, when the plate line is decoded (pulse driven), high CR (capacitance and resistance) is required. So, the plate line is operated with a delay. In this instance, it is impossible to read all data written in the memory cell. There is also a fear that the data can not be written completely in the cell.
There is another problem, namely, when a non-volatile ferroelectric memory is mounted on a memory card etc., if a thin memory card is used, external physical stress is easily applied. As a result, a problem could arise wherein the hysteresis property (which is involved in data cohesion properties) may be degraded.
It is well known, that the shape of a hysteresis loop greatly changes with temperature. In other words, a hysteresis loop at high temperature (e.g. 80.degree. C.) is smaller, compared to the shape of the loop at low temperature, which makes the value of polarization small. The ferroelectric memory employs polarization for data holding. Accordingly, the existence of a heat source within the chip leads to deterioration in the data holding property, particularly when a non-volatile ferroelectric memory is mounted on a memory card. Heat, which dissipates from a power supply circuit or a rectifier circuit, will have an adverse effect on the ferroelectric memory data holding property.
FIG. 2 shows a hysteresis loop for ferroelectric material applicable to the FRAM (ferroelectric random access memory) memory cell using the ferroelectric layer for a capacitor. For read and write operations, it is necessary to change operations along with the loop in the a.fwdarw.b.fwdarw.c.fwdarw.d sequence. Actually, however, a current flows only around points b and d. A polarization of the ferroelectric layer is inverted only at slightly flows at b and d. Accordingly, even when the plate line (PL) is activated as shown in FIG. 3(a), little current flows when the polarization is in the a and c areas. In the b and d areas in contrast, a pulse-like current flows, i.e., (FIG. 3(b)). If high current flows for such an extremely short time, the maximum current rate will increase. As a result, there is a possibility that various malfunctions would occur due to power fluctuations (noise) or reference voltage fluctuation, which has occurred therein.